Semiconductor device

ABSTRACT

According to one embodiment, a semiconductor device includes an interface, a power supply, a driver, and a switch section. The interface includes a first MOSFET and converts a terminal switch signal of input serial data into parallel data. The first MOSFET is provided on the SOI substrate and has a back gate in a floating state. The power supply includes a second MOSFET and generates an ON potential higher than a potential of a power supply to be supplied to the interface. The second MOSFET is provided on the SOI substrate and has a back gate connected to a source. The driver includes a third MOSFET and outputs a control signal for controlling the ON potential to be in a high level according to the parallel data. The third MOSFET is provided on the SOI substrate and has a back gate connected to a source.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromthe prior Japanese Patent Application No. 2010-265311, filed on Nov. 29,2010; the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a semiconductor device.

BACKGROUND

A semiconductor switch for opening and closing a circuit can be used forvarious electric devices. For example, in a radio frequency circuit of amobile telephone, a transmitting circuit and a receiving circuit areselectively connected to a common antenna through a radio frequencyswitching circuit. It is used that a MOSFET (Metal Oxide SemiconductorField Effect Transistor) is formed on an SOI (Silicon On Insulator)substrate for a switching device of such radio frequency switchingcircuit. Moreover, a terminal switch signal for switching connectionbetween terminals is transmitted in parallel.

However, to meet a demand for an increase in the number of radiofrequency terminals with an increase in frequency band, orsystemization, high speed serial transmission of terminal switch signalhas been considered. In the meantime; however, an increase in powerconsumption has been a concern.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating a configuration of asemiconductor device according to a first embodiment;

FIG. 2 is a circuit diagram illustrating a configuration of a switchsection of the semiconductor device shown in FIG. 1;

FIG. 3 is a circuit diagram illustrating a configuration of a levelshifter of a driver of the semiconductor device shown in FIG. 1;

FIG. 4 is a cross-sectional view of a transistor of the semiconductordevice;

FIG. 5 is a plan view illustrating a layout of a first MOSFET of thesemiconductor device;

FIG. 6 is a plan view illustrating a layout of a second MOSFET of thesemiconductor device;

FIG. 7 is a plan view illustrating a layout of a fourth MOSFET of thesemiconductor device;

FIG. 8 is a block diagram illustrating a configuration of asemiconductor device according to a second embodiment; and

FIG. 9 is a plan view illustrating a configuration of a semiconductordevice according to a third embodiment.

DETAILED DESCRIPTION

In general, according to one embodiment, a semiconductor device includesan interface, a power supply, a driver, and a switch section. Theinterface includes a first MOSFET and converts a terminal switch signalof input serial data into parallel data. The first MOSFET is provided onthe SOI substrate and has a back gate in a floating state. The powersupply includes a second MOSFET and generates an ON potential higherthan a potential of a power supply to be supplied to the interface. Thesecond MOSFET is provided on the SOI substrate and has a back gateconnected to a source. The driver includes a third MOSFET and outputs acontrol signal for controlling the ON potential to be in a high levelaccording to the parallel data. The third MOSFET is provided on the SOIsubstrate and has a back gate connected to a source.

Embodiments will now be described in detail with reference to thedrawings. The drawings are schematic or conceptual; and therelationships between the thickness and width of portions, theproportions of sizes among portions, etc., are not necessarily the sameas the actual values thereof. Further, the dimensions and proportionsmay be illustrated differently among the drawings, even for identicalportions. In the specification and the drawings of the application,components similar to those described in regard to a drawingthereinabove are marked with like reference numerals, and a detaileddescription is omitted as appropriate.

First Embodiment

FIG. 1 is a block diagram illustrating a configuration of asemiconductor device according to a first embodiment.

As shown in FIG. 1, a semiconductor device 1 is provided on an SOIsubstrate 2 with a common terminal ANT, radio frequency terminals RF1 toRFk (k being a natural number of 2 or more) and a switch section 3 forswitching connection between terminals. The switch section 3 switchesconnection between terminals in response to control signals Con1a-Conka,Con1b-Conkb output from a driver 5.

An interface 4 is provided on the SOI substrate 2, and converts aterminal switch signal of serial data input to a switch signal terminalSDATA into 2k-bit parallel data D1a-Dka, D1b-Dkb in which each bit is adifferential signal. Here, k-bit parallel data D1b-Dkb are inverted dataof k-bit parallel data D1a-Dka respectively.

In the interface 4, for example, a serial-to-parallel converter isprovided for converting serial data into parallel data. The converted2k-bit parallel data D1a-Dka, D1b-Dkb are held in a hold circuit such asa latch circuit or the like, and are output to the driver 5.

As will be explained in FIG. 5, the interface 4 includes a first MOSFET7 operable at high speed, and is supplied with a power supply potentialVdd1. In FIG. 1, an N-channel type MOSFET (hereinafter NMOS) isillustrated as the first MOSFET 7. However, a P-channel type MOSFET(hereinafter PMOS) may be adopted.

The parallel data D1a-Dka, D1b-Dkb are level-shifted in the driver 5provided on the SOI substrate 2 to be output as 2k-bit control signalsCon1a-Conka, Con1b-Conkb. Here, k-bit control signals Con1b-Conkb areinverted signals of Con1a-Conka respectively.

The driver 5 supplies an ON potential Von and an OFF potential Voff.

Here, the ON potential Von is a high level potential of control signalsCon1a-Conka, Con1b-Conkb. The ON potential Von is to be applied to agate of each FET of the switch section 3 to turn it ON, and has apotential to make an ON resistance sufficiently low value, for example,3.5 V.

On the other hand, the OFF potential Voff is a low level potential ofthe control signals Con1a-Conka, Con1b-Conkb. The OFF potential is to beapplied to the gate of each FET of the switch section 3 to turn it OFF,and has a potential to sufficiently maintain the OFF state even if aradio frequency signal is superimposed. The OFF potential is, forexample, −1.5 V.

The ON potential Von and the OFF potential Voff are supplied from apower supply 6 provided on the SOI substrate 2. The power supply 6 issupplied externally with a positive power supply potential Vdd2. Thepower supply 6 generates an ON potential Von which is higher than thepower supply potential Vdd2, and a negative OFF potential Voff. The ONpotential Von is higher than the power supply potential Vdd1 of theinterface 4. The power supply 6 includes, for example, an oscillator, acharge pump and the like, and is formed on the SOI substrate 2.

As explained in FIG. 6, in order to output an ON potential Von in a highlevel, the drive 5 includes a second MOSFET 8 of high breakdown voltage.On the other hand, in order to generate the ON potential Von and the OFFpotential Voff, the power supply 6 includes a third MOSFET 9 of highbreakdown voltage. In FIG. 1, the NMOS and the PMOS are illustrated asthe MOSFET 8 and the MOSFET 9, respectively. However, either of the PMOSand the NMOS may be adopted for the second and the third MOSFETs 8 and9.

The semiconductor device 1 is a switch of SPkT (Single-Pole k-Throw)that switches connection between the common terminal ANT and the radiofrequency terminals RF1-RFk in response to a terminal switch signal ofserial data input to the switch signal terminal SDATA.

Next, each section will be explained.

FIG. 2 is a circuit diagram illustrating a configuration of a switchsection of the semiconductor device shown in FIG. 1.

As shown in FIG. 2, a configuration of an SP6T switch is illustrated inthe switch section 3a. First switching elements 13a, 13b, 13c, 13d, 13eand 13f are connected respectively between the common terminal ANT andradio frequency terminals RF1, RF2, RF3, RF4, RF5 and RF6. By turning ONthe first switching elements 13a, 13b, 13c, 13d, 13e and 13f,transmission paths are formed between the common terminal ANT, and theradio frequency terminals RF1, RF2, RF3, RF4, RF5 and RF6 respectively.

The first switching element 13a includes n-stage (n is a natural number)through FETs T11, T12, . . . , T1n connected in series. To respectivegates of the through FETs T11, T12, . . . , T1n, a control signal Con1ais input through resistors for preventing leakage of radio frequency.The first switching elements 13b, 13c, 13d, 13e and 13f respectivelyhave the same configuration as the first switching element 13a. To thefirst switching elements 13b, 13c, 13d, 13e and 13f, control signalsCon2a, Con3a, Con4a, Con5a and Con6a are input respectively.

Second switching elements 14a, 14b, 14c, 14d, 14e and 14f are connectedrespectively between the radio frequency terminals RF1, RF2, RF3, RF4,RF5 and RF6 and ground GND. These second switching elements 14a, 14b,14c, 14d, 14e and 14f release leakage current respectively flowing inthe radio frequency terminals RF1, RF2, RF3, RF4, RF5 and RF6 to theground when the first switching devices 13a, 13b, 13c, 13d, 13e and 13fare turned OFF respectively. Thereby, improving isolation is achievedamong the radio frequency terminals RF1, RF2, RF3, RF4, RF5 and RF6.

The second switching element 14a includes m-stage (m is a naturalnumber) shunt FETs S11, S12, . . . , S1m connected in series. Torespective gates of the shunt FETs S11, S12, . . . , S1m, a controlsignal Con1b is input through resistors for preventing leakage of radiofrequency. The second switching elements 14b, 14c, 14d, 14e and 14frespectively have the same configuration as the second switching element14a. To the second switching elements 14b, 14c, 14d, 14e and 14f,control signals Con2b, Con3b, Con4b, Con5b and Con6b are inputrespectively.

For example, to allow conduction between the radio frequency terminalRF1 and the common terminal ANT, the first switching element 13a, whichis between the radio frequency terminal RF1 and the common terminal ANT,is turned ON, and the second switching element 14a, which is between theradio frequency terminal RF1 and the ground, is turned OFF. Namely, allthe through FETs T11, T12, . . . , Tin of the first switching element13a are turned ON, and all the shunt FETs S11, S12, . . . , S1m of thesecond switching element 14a are turned OFF.

At the same time, all the other first switching elements 13b, 13c, 13d,13e and 13f, which are respectively provided between the radio frequencyterminals RF2, RF3, RF4, RF5 and RF6 and the common terminal ANT, areturned OFF, and all the other second switching elements 14b, 14c, 14d,14e and 14f, which are respectively provided between the radio frequencyterminals RF2, RF3, RF4, RF5 and RF6 and the ground, are turned ON.Namely, all the through FETs of the first switching elements 13b, 13c,13d, 13e and 13f are turned OFF, and all the shunt FETs of the secondswitching elements 14b, 14c, 14d, 14e and 14f are turned ON.

In the above case, the control signal Con1a is set to the ON potentialVon, the control signals Con2b, Con3b, Con4b, Con5b and Con6b are set tothe ON potential Von, the control signal Con1b is set to the OFFpotential Voff, and the control signals Con2a, Con3a, Con4a, Con5a andCon6a are set to the OFF potential Voff.

In FIG. 2, the SP6T switch is illustrated for the configuration of theswitch section 3a. However, a switch of other configuration is alsoapplicable, and a configuration of an wPkT switch (w is a naturalnumber, and K is a natural number of 2 or more) may be adopted.

Referring back to FIG. 1, the driver 5 has level shifters 12a-12k in thenumber of k (k is a natural number of 2 or more) that is the same numberas the number of the radio frequency terminals RF1-RFk. Since all thelevel shifters 12a to 12k have the same configuration, the configurationof the level shifter 12a will be explained here.

FIG. 3 is a circuit diagram illustrating a configuration of a levelshifter of the driver of the semiconductor device shown in FIG. 1.

The level shifter 12a has a first-stage level shifter 15a and asecond-stage level shifter 16a. The first-stage level shifter 15a has apair of NMOSs N11 and N12, and a pair of PMOSs P11 and P12. Thesecond-stage level shifter 16a has a pair of PMOSs P21 and P22, and apair of NMOSs N23 and N24.

Sources of the NMOSs N11 and N12 are connected to the groundrespectively. Gates of the NMOSs N11 and N12 respectively receive dataD1a and D1b output from the interface 4 of the first stage. The data D1aand D1b are 2-bit differential data of 2k-bit differential parallel dataD1a-Dka, D1b-Dkb output from the interface 4. The data D1b is inverteddata of data D1a.

Drains of the NMOSs N11 and N12 are connected to drains of the PMOSs P11and P12 respectively. The sources of the PMOSs P11 and P12 receive theON potential Von supplied respectively from the power supply 6 through ahigh potential power supply line 10. The gate of the PMOS P11 isconnected to the drain of the PMOS P12, and these are connected to oneoutput line OUT1B of a differential output from the first-stage levelshifter 15a. The gate of the PMOS P12 is connected to the drain of thePMOS P11, and these are connected to the other output line OUT1A of thedifferential output from the first-stage level shifter 15a.

The output lines OUT1A and OUT1B are respectively connected to the gatesof the PMOSs P21 and P22 of the second-stage level shifter 16a. Theoutput signal from the first-stage level shifter 15a is input to thesecond-stage level shifter 16a through the output lines OUT1A and OUT1B.The ON potential Von is supplied from the power supply 6 to therespective sources of the PMOSs P21 and P22 through the high potentialpower supply line 10.

The drain of the PMOS P21 is connected to the drain of the NMOS N23, andthese drains are further connected to the output line OUTA respectively.The drain of the PMOS P22 is connected to the drain of the NMOS N24, andthese drains are further connected to the output line OUTB. The ONpotential Von and the OFF potential Voff of the control signals Con1aand Con1b to be respectively output to the output lines OUTA and OUTBare supplied to the respective gates of the through FETs and the shuntFETs of the switch section 3a shown in FIG. 2.

The input level of the differential data D1a and D1b to be input to thefirst-stage level shifter 15a is a high level of Vdd1 (for example, 1.8V) and a low level of 0 V, and these differential data D1a and D1b aresupplied from the interface 4 shown in FIG. 1. For example, 3.5 V issupplied as the ON potential Von to the high potential power supply line10.

For example, when the differential data D1a is input with high level(1.8 V) and the differential data D1b is input with low level (0 V), thepotential of the output line OUT1A is set to low level (0 V), and thepotential of the output line OUT1B is set to 3.5 V, which is equal tothe ON potential Von. In other words, the output amplitude in thefirst-stage level shifter 15a is approximately 3.5 V, from 0 to Von.

The second-stage level shifter 16a receives the output signal of thefirst-stage level shifter 15a. In the same manner as the first-stagelevel shifter 15a, the ON potential Von is supplied to the second-stagelevel shifter 16a through the high potential power supply line 10, andthe OFF potential Voff is supplied to the second-stage level shifter 16athrough the low potential power supply line 11.

The ON potential Von is, for example, 3.5 V. The OFF potential is, forexample, −1.5 V.

For example, when the output line OUT1A is at low level (0 V) and theoutput line OUT1B is at high level (3.5 V), the potential of the outputline OUTA, i.e., the potential of the control signal Con1a is set to 3.5V, which is equal to the ON potential Von, and the potential of theoutput terminal OUTB, i.e., the potential of the control signal Con1b isset to −1.5 V, which is equal to the OFF potential Voff. Accordingly,3.5 V as the ON potential Von and −1.5 V as the OFF potential Voff canbe supplied to the gates of the through FETs and shunt FETs of theswitch section 3 shown in FIG. 2, thereby driving the switch section 3.

The first-stage level shifter 15a transforms the potential of the highlevel into the ON potential Von. The second-stage level shifter 16atransforms the potential of the low level into the OFF potential Voff.Accordingly, the level shifter 12a transforms an input signal in whichthe high level is the power supply potential Vdd1 and the low level is 0V into the control signal Con1a and the control signal Con1b in whichthe high level is the ON potential Von and the low level is the OFFpotential Voff, respectively.

In the level shifter 15a, the gate-source voltage and the drain-sourcevoltage of each FET of the first-stage level shifter 15a might become3.5 V, which is equal to the ON potential Von. Moreover, the gate-sourcevoltage and the drain-source voltage of each FET of the second-stagelevel shifter 16a might become 5.0 V, which is equal to the ON potentialVon—the OFF potential Voff. Therefore, the level shifter 15a isconfigured by FETs of high breakdown voltage.

As explained with reference to FIG. 6, each FET of the level shifter 15ais configured by the second MOSFET 8.

Various configurations exist as a circuit configuration of the levelshifter 15a other than the circuit configuration illustrated in FIG. 5.For the level shifter of the semiconductor device 1, any circuitconfiguration may be adopted as long as the function of level shiftingthe high level to the ON potential Von higher than the positive powersupply potential Vdd2 to be supplied externally and level shifting thelow level to the negative OFF potential Voff.

Referring back to FIG. 1, the interface 4 transforms a terminal switchsignal of serial data input to the switch signal terminal SDATA into2k-bit parallel data D1a-Dka, D1b-Dkb in which each bit is adifferential signal.

The serial data is input to the switch signal terminal SDATA in syncwith a clock signal input to a clock terminal SCLK.

The serial data and the clock signal are output from a microprocessor,for example. The clock signal has been sped up as the microprocessorspeeds up. On the other hand, there is a restriction in allowablecurrent consumption in the interface 4 as the power consumption becomeslow. Therefore, the power supply potential Vdd1 of lower potential issupplied to the interface 4 compared to the case of the switch section 3or the driver 5.

FIG. 4 is a cross-sectional view of a transistor of the semiconductordevice.

In FIG. 4, a cross-sectional view of the NMOS provided on the SOIsubstrate 2 is shown schematically.

In a silicon (Si) substrate 60, an embedded oxide film layer 62 isprovided. On the embedded oxide film layer 62, a source region 68 and adrain region 72 are provided so as to sandwich an SOI layer 64 inbetween. An element isolation layer 74 is provided on the embedded oxidefilm layer 62 so as to surround the source region 68, the SOI layer 64and the drain region 72. Further, a gate electrode 70 is provided on thesource region 68, the SOI layer 64 and the drain region 72 via a gateoxide film 66.

The lower side of a channel of the first MOSFET 7 is the embedded oxidefilm layer 62, and is insulated from the silicon substrate 60 whichserves as a support substrate. The lateral side of the channel isinsulated and isolated from other element by the element isolation layer74. Furthermore, a back gate 80 is in an electrically floating state.

Neither of the source electrode and the drain electrode is shown in thefigure. Moreover, when the first MOSFET 7 is the N-channel type, theback gate 80 is the P-type, and the source region 68 and drain region 72are the N-type. On the other hand, when the first MOSFET 7 is theP-channel type, the back gate 80 is the N-type, and the source region 68and drain region 72 are the P-type.

For the MOSFET, various layout shapes are available, and thecharacteristics of the MOSFET differ for each layout shape.

FIG. 5 is a plan view illustrating a layout of a first MOSFET of thesemiconductor device.

As shown in FIG. 5, the first MOSFET 7 has contacts 82 and 84 providedin the source region 68 and the drain region 72 respectively, and thesecontacts 82 and 84 are electrically connected to the source electrodeand the drain electrode (not shown) respectively. The back gate 80 (notshown) is in the floating state. The first MOSFET 7 is assumed to have agate length Lg1 and a gate width Wg1.

FIG. 6 is a plan view illustrating a layout of a second MOSFET of thesemiconductor device.

As shown in FIG. 6, the second MOSFET 8 has the contacts 82 and 84provided in the source region 68 and the drain region 72 respectively,and these contacts 82 and 84 are electrically connected to the sourceelectrode and the drain electrode (not shown) respectively.

Moreover, the back gate 80 is drawn to above and below the source region68, and is electrically connected to a back gate electrode (not shown).The second MOSFET 8 is assumed to have a gate length Lg2 and a gatewidth Wg2.

The third MOSFET 9 shown in FIG. 1 has the same layout shape as thesecond MOSFET 8.

FIG. 7 is a plan view illustrating a layout of a fourth MOSFET of thesemiconductor device.

As shown in FIG. 7, a fourth MOSFET 17 has contacts 82 and 84 providedin the source region 68 and the drain region 72 respectively, and thesecontacts 82 and 84 are electrically connected to the source electrodeand the drain electrode (not shown) respectively. The gate electrode 70is formed into an H-shape.

The back gate 80 is drawn to above and below the gate electrode 70, andhas a back gate contact 86 provided thereon. The back gate 80 iselectrically connected to a back gate electrode (not shown).

The first MOSFET 7 is a MOSFET generally used in a bulk CMOS. The firstMOSFET 7 has excellent layout efficiency and a small gate parasiticcapacitance as compared to the second, the third and the fourth MOSFETs8, 9 and 17, thus realizing shorter delay time and smaller powerconsumption product. However, since the back gate 80 is in the floatingstate, the drain breakdown voltage is low.

Each of the second, the third and the fourth MOSFETs 8, 9 and 17 has theback gate electrode, and realizes a high drain breakdown voltage byconnecting the back gate 80 to the source region 68. However, to realizethe high drain breakdown voltage, the back gate 80 needs to have a smallparasitic resistance. Thus, the ratio of the gate width to the gatelength Wg2/Lg2 needs to be set small. For example, approximately Wg2=1μm and Lg2=1 μm.

Therefore, when designing the circuit, in order to realize a desiredratio of Wg2/Lg2, it is necessary to lay out a large number of unit FETsof Wg2=1 μm and Lg2=1 μm connected in parallel, resulting in poor layoutefficiency. Moreover, the parasitic capacitance per unit gate width alsobecomes as large as several times that of the first MOSFET 7.

As described above, in the semiconductor device 1, the driver 5 and thepower supply 6 are configured by the second MOSFET 8, the third MOSFET 9or the fourth MOSFET 17 which mainly has the back gate 80 connected tothe source region 68. On the other hand, the interface 4 is configuredmainly by the first MOSFET 7.

The ON potential Von is generated in the power supply 6, and therelationship of power supply potential Vdd1<ON potential Von holds.

For the power supply potential Vdd2 to be supplied to the power supply6, a maximum rated value is 4V, for example. In response, at least theportion of the power supply 6, which requires high breakdown voltage, isconfigured by the third MOSFET 9 or the fourth MOSFET 17 which has theback gate 80 connected to the source region 68. A high maximum ratedvalue can be achieved due to the high drain breakdown voltage. Here, theentire power supply 6 may be configured by the third MOSFET 9 or thefourth MOSFET 17.

As described, the driver 5 receives the ON potential Von as a highpotential power supply and the OFF potential Voff as a low potentialpower supply. The output amplitude becomes Von-Voff. For example, whenit is assumed that ON potential Von=3.5 V and OFF potential Voff=−1.5 V,it is necessary to output control signals Con1a-Conka, Con1b-Conkbhaving a logical amplitude of 5V.

In response, at least the portion of the driver 5 which requires highbreakdown voltage is configured by the third MOSFET 9 having the samestructure as the second or the fourth MOSFET 8 or 17, which has the backgate 80 connected to the source region 68. Due to the high drainbreakdown voltage thereof, a logical amplitude of 5V can be realized.Here, the entire driver 5 may be configured by the third MOSFET 9 or thefourth MOSFET 17.

For the driver 5 and the power supply 6, since a high speed operation isnot required, the third MOSFET 9 having large parasitic capacitance maybe used without problem.

The interface 4 needs to operate, for example, at a clock frequency of26 MHz and a low consumption current of 0.5 mA. Here, at least a portionof the interface 4 which requires high speed operation is configured bythe first MOSFET 7, thereby realizing high speed and low powerconsumption at the same time.

Additionally, the power supply potential Vdd1 to be supplied to theinterface 4 is 1.8V, for example, which is lower than the ON potentialVon. Therefore, even the first MOSFET 7 having relatively low drainbreakdown voltage may be adopted without problem.

Moreover, the entire interface 4 may be configured by the first MOSFET7.

As described, according to the semiconductor device 1, even when theterminal switch signal, that controls the connection state of the switchsection 3 is input as serial data, it is possible to operate at highspeed with low current consumption.

Additionally, the gate length Lg2 of the second MOSFET 8 included in thedriver 5 is set longer than the gate length Lg1 of the first MOSFET 7included in the interface 4, and the gate length Lg3 of the third MOSFET9 included in the power supply 6 is set longer than the gate length Lg1of the first MOSFET 7.

In the first MOSFET 7 included in the interface 4, the gate length ofthe PMOS and the gate length of the NMOS are assumed to be Lg1p and Lg1nrespectively. In the second MOSFET 8 included in the driver 5, the gatelength of the PMOS and the gate length of the NMOS are assumed to beLg2p and Lg2n respectively. In the third MOSFET 9 included in the powersupply 6, the gate length of the PMOS and the gate length of the NMOSare assumed to be Lg3p and Lg3n respectively.

Then, the gate length of each FET is set so as to satisfy the followinginequalities (1) to (4):Lg1p<Lg2p   (1)Lg1n<Lg2n   (2)Lg1p<Lg3p   (3)Lg1n<Lg3n   (4)

Additionally, the gate length Lg3 of the third MOSFET 9 may be set equalto the gate length Lg2 of the second MOSFET 8. Namely, each gate lengthmay be set to satisfy the relationship of Lg3p=Lg2p and Lg3n=Lg2n.

For example, the gate length of each FET may be set so as to satisfy theequalities (5):Lg1=Lg1p=Lg1n=0.25 μmLg2=Lg2p=Lg2n=1 μmLg3=Lg3p=Lg3n=1 μm   (5)

By setting the gate length Lg2 and the gate length Lg3 of the secondMOSFET 8 and the third MOSFET 9 to 1 μm, it is possible to improve thereliability and realize a higher breakdown voltage of each FET includedin the driver 5 and the power supply 6. On the other hand, by settingthe gate length Lg1 of the first MOSFET 7 included in the interface 4 toa small value of 0.25 μm, it is possible to realize a higher speedoperation. Moreover, in the interface 4, it is possible to increase aphase margin of the serial data in response to a clock signal to beinput to the clock terminal SCLK.

By setting the gate length of the first, the second and the thirdMOSFETs 7, 8 and 9 as described above, it is possible to realize a stillhigher speed operation of the interface 4 and to improve reliability ofthe driver 5 and the power supply 6.

Additionally, an absolute value of the threshold voltage Vth2 of thesecond MOSFET 8 is set higher than that of the threshold voltage Vth1 ofthe first MOSFET 7, and an absolute value of the threshold voltage Vth3of the third MOSFET 9 is set higher than that of the threshold voltageVth1 of the first MOSFET 7.

In the first MOSFET 7 included in the interface 4, the threshold voltageof the PMOS and the threshold voltage of the NMOS are assumed to beVth1p and Vth1n respectively. In the second MOSFET 8 included in thedriver 5, the threshold voltage of the PMOS and the threshold voltage ofthe NMOS are assumed to be Vth2p and Vth2n respectively. In the thirdMOSFET 9 included in the power supply 6, the threshold voltage of thePMOS and the threshold voltage of the NMOS are assumed to be Vth3p andVth3n respectively.

Then, the threshold voltage of each FET is set so as to satisfy thefollowing inequalities (6) to (9):|Vth1p|<|Vth2p|  (6)Vth1n<Vth2n   (7)|Vth1p|<|Vth3p|  (8)Vth1n<Vth3n   (9)

Additionally, the threshold voltage Vth3 of the third MOSFET 9 may beset equal to the threshold voltage Vth2 of the second MOSFET 8. Namely,each threshold voltage may be set so as to satisfy the relationship ofVth3p=Vth2p and Vth3n=Vth2n.

For example, the threshold voltage of each FET may be set so as tosatisfy the equalities (10):Vth1p=−0.3 VVth1n=0.3 VVth2p=Vth3p=−0.6 VVth2n=Vth3n=0.6 V   (10)

By making the absolute value of the threshold voltage Vth1 of the firstMOSFET 7 included in the interface 4 smaller, it is possible to realizea higher speed operation thereof. Moreover, it is possible to increase aphase margin of the serial data in response to a clock signal to beinput to the clock terminal SCLK in the interface 4.

Additionally, by making larger the respective absolute values of thethreshold voltages Vth2 and Vth3 of the second and the third MOSFETs 8and 9 included in the driver 5 and the power supply 6 respectively, itis possible to increase a noise margin. Consequently, it is possible toimprove noise immunity with respect to a radio frequency signal thatleaks from the switch section 3.

Additionally, in the period in which a radio frequency signal is beinginput, the interface 4 only functions to output data held in the holdingcircuit such as a latch circuit, for example, provided in its outputsection. Thus, even if the noise margin of the CMOS logic circuit whichconfigures the circuit is small, there is no concern of a falseoperation due to a radio frequency noise.

Thus, by setting the threshold voltages of the first, the second and thethird MOSFETs 7, 8 and 9 as described above, it is possible to reduce adanger of the false operation due to a radio frequency signal whilerealizing high speed operation.

Second Embodiment

FIG. 8 is a block diagram illustrating a configuration of asemiconductor device according to a second embodiment. In FIG. 8, amember used in common with the semiconductor device 1 shown in FIG. 1 isdenoted by the same reference numeral.

As shown in FIG. 8, a semiconductor device 1a includes the switchsection 3, an interface 4a, the driver 5, the power supply 6 and adecoder 18, which are provided on the SOI substrate 2.

In the semiconductor device 1a, the interface 4 of the semiconductordevice 1 shown in FIG. 1 is replaced by the interface 4a, and thedecoder 18 is further provided. The decoder 18 decodes input i-bitparallel data Vc1-Vci into 2k-bit parallel data D1a-Dka, D1b-Dkb of adifferential signal. Here, i is a minimum integer of 1 or more thatsatisfies the relationship of i≧log₂k.

Therefore, the serial data encoded to i-bit can be input to the switchsignal terminal SDATA as a terminal switch signal. The interface 4aconverts the encoded i-bit serial data into i-bit parallel data Vc1-Vci.

For the decoder 18, the power supply potential Vdd1 can be used.Further, an internal power supply circuit may be provided, forgenerating a power supply potential to be supplied to the decoder 18from the power supply potential Vdd2.

Additionally, for the MOSFET 19 which configures the decoder 18, alayout of any one of the first MOSFET 7, the second MOSFET 8 and thefourth MOSFET 17 may be adopted. This is because a relatively low powersupply potential is supplied to the decoder 18, and a high speedoperation is not required.

The driver 5 and the power supply 6 include the second MOSFET 8 and thethird MOSFET 9, each having the back gate 80 connected to the sourceregion 68 as in the case of the semiconductor device 1.

The interface 4 includes the first MOSFET 7 that has the back gate 80 inthe floating state, and the relationship of the power supply potentialVdd1<the ON potential Von holds.

According to the semiconductor device 1a, the number of stages of theholding circuit, for example, a shift register, a latch circuit, etc.,of the interface 4a that operates at high speed is decreased to i-bit.Thus, it is possible to realize further reduction in power consumption.

For example, assuming the case of k=8 bit, the i-bit is 3-bit. In thesemiconductor device 1 shown in FIG. 1, the interface 4 outputsdifferential data of 8×2=16 bit of D1a-D8a, D1b-D8kb. These signals aregenerated and held, for example, in the eight shift registers and latchcircuits.

On the other hand, according to the semiconductor device 1a, since thedecoder 18 is provided in the second stage of the interface 4a, allrequired is to generate the encoded data Vc1-Vci. For example, in thecase of k=8 bit, i=3 bit of data Vc1, Vc2 and Vc3 are good enough. Thus,for the number of the shift registers and the latch circuits in theinterface 4a, three would be enough.

As described, in the semiconductor device 1a, since the number of thefirst MOSFETs 7 included in the interface 4a is reduced, it is possibleto further reduce power consumption.

Therefore, according to the semiconductor device 1a, it is possible torealize with ease a semiconductor device in which a signal forcontrolling the connection state of the switch section 3 is seriallytransmitted, and to reduce power consumption in the serial transmission.

Third Embodiment

FIG. 9 is a plan view illustrating a configuration of a semiconductordevice according to a third embodiment.

In FIG. 9, a layout of a semiconductor device 1b is shown schematically.In FIG. 9, a member used in common with the semiconductor device 1 shownin FIG. 1 is denoted by the same reference numeral.

A semiconductor device 1b includes the interface 4, the driver 5, thepower supply 6 and pads 20a and 20b, which are provided on the SOIsubstrate 2. The switch section 3, interface 4, the driver 5, and thepower supply 6 respectively have the same circuit configuration as thesemiconductor device 1 shown in FIG. 1.

In the semiconductor device 1b, the interface 4 is provided in an areabetween the pad 20a and the pad 20b. Here, the pad 20a and the pad 20bare provided for the ground GND and the power supply potential Vdd1respectively. Here, either one of the pads 20a and 20b is provided forthe ground GND, and the other one is provided for receiving the powersupply potential Vdd1.

The interface 4 includes the first MOSFET 7 having excellent layoutefficiency. Thus, it is sufficiently possible to lay it out in thenarrow area between the pads. Therefore, there is no increase in a chiparea for adopting the serial interface of the terminal switch signal.Moreover, since the power supply pad and the ground pad are provided inclose vicinity, it is possible to perform a high speed operation understable conditions.

Therefore, according to the semiconductor device 1b, it is possible toeasily realize a semiconductor device in which a signal for controllingthe connection state of the switch section 3 is serially transmitted,and to maintain the same chip area as that of the semiconductor in whicha parallel transmission is performed.

For the semiconductor devices 1 and 1a, explanations have been giventhrough the case of inputting a terminal switch signal of serial data tothe switch signal terminal SDATA. However, for the serial data, dataother than the k-bit of the radio frequency terminals RF1-RFk or encodedi-bit data may be added.

For example, a microprocessor or the like generally outputs data to aplurality of elements. Therefore, to switch signal terminals SDATA, aplurality of elements may be connected, or serial data having addedthereto an address for identifying each element may be input. In thiscase, the interfaces 4 and 4a identify the address and convert the inputserial data into parallel data for output.

Furthermore, the switch signal terminal SDATA may be connected to abi-directional bus capable of receiving and outputting. In this case,the interfaces 4 and 4a may convert parallel data into serial data tooutput it to the switch signal terminal SDATA.

While certain embodiments have been described, these embodiments havebeen presented by way of example only, and are not intended to limit thescope of the inventions. Indeed, the novel embodiments described hereinmay be embodied in a variety of other forms; furthermore, variousomissions, substitutions and changes in the form of the embodimentsdescribed herein may be made without departing from the spirit of theinventions. The accompanying claims and their equivalents are intendedto cover such forms or modifications as would fall within the scope andspirit of the invention.

What is claimed is:
 1. A semiconductor device, comprising: an interfaceincluding a first MOSFET and converting a terminal switch serial inputsignal of input serial data into parallel data signals, the first MOSFETbeing provided on an SOI a silicon-on-insulator substrate and having aback gate in a floating state and; a power supply including a secondMOSFET and generating an ON output potential that is higher than apotential of a power supply potential to be supplied to the interface,the second MOSFET being provided on an SOI the silicon-on-insulatorsubstrate and having a back gate connected to a source of the secondMOSFET; a driver including a third MOSFET and outputting a controlsignal for controlling the ON potential to be in a high level accordingto the parallel data signals, the third MOSFET provided on an SOI thesilicon-on-insulator substrate and having a back gate connected to asource of the third MOSFET; and a switch section provided on the SOIsilicon-on-insulator substrate and switching connection connectionsbetween a plurality of terminals by inputting according to the controlsignal.
 2. The device according to claim 1, wherein a gate length of thesecond MOSFET is longer than that a gate length of the first MOSFET. 3.The device according to claim 1, wherein a gate length of the third,MOSFET is longer than that a gate length of the first MOSFET.
 4. Thedevice according to claim 1, wherein an absolute value of a thresholdvoltage of the second MOSFET is larger than that of a threshold voltageof the first MOSFET.
 5. The device according to claim 1, wherein anabsolute value of a threshold voltage of the third MOSFET is larger thanthat of a threshold voltage of the first MOSFET.
 6. The device accordingto claim 1, further comprising: a decoder decoding the parallel data. 7.The device according to claim 1, wherein the back gate of the secondMOSFET is drawn to both on two sides of the source in a verticaldirection to the SOI substrate of the second MOSFET, the two sides ofthe source of the second MOSFET being spaced from each other in adirection parallel to a gate width direction of the second MOSFET. 8.The device according to claim 7, wherein the second MOSFET is formed inan H-shape in the vertical direction to the SOI substrate.
 9. The deviceaccording to claim 1, wherein the back gate of the third MOSFET is drawnto both on two sides of the source in a vertical direction to the SOIsubstrate of the third MOSFET, the two sides of the source of the thirdMOSFET being spaced from each spaced from each other in a directionparallel to a gate width direction of the third MOSFET.
 10. The deviceaccording to claim 9, wherein the third MOSFET is formed in an H-shapein the vertical direction to the SOI substrate.
 11. The device accordingto claim 1, wherein the third MOSFET has the same planar layout shape asthe second MOSFET.
 12. The device according to claim 1, wherein thefirst MOSFET has a lower breakdown voltage than the second MOSFET. 13.The device according to claim 1, wherein the first MOSFET has a lowerbreakdown voltage than the third MOSFET.
 14. The device according toclaim 1, wherein the first MOSFET has a smaller layout area than thesecond MOSFET.
 15. The device according to claim 1, wherein the firstMOSFET has a smaller layout area than the third MOSFET.
 16. The deviceaccording to claim 1, further comprising: a power supply pad provided onboth sides of the interface on the SOI silicon-on-insulator substrate ona first side of the interface, the power supply pad for supplying powerto the interface; and a ground pad provided on the silicon-on-insulatorsubstrate on a second side of the interface opposite the first side. 17.A semiconductor device, comprising: an interface provided on asilicon-on-insulator substrate and configured to convert serial datainto parallel data, the interface including a first MOSFET having a backgate with a floating potential; a first power supply provided on thesilicon-on-insulator substrate and configured to generate a firstpotential that is greater than a second potential, the second potentialbeing supplied to the interface by a second power supply, the firstpower supply including a second MOSFET having a back gate connected to asource of the second MOSFET; a driver provided on thesilicon-on-insulator substrate and including a third MOSFET having aback gate connected to a source of the third MOSFET, the driverconfigured to generate a plurality of control signals based on the firstpotential according to the parallel data; and a switch section providedon the silicon-on-insulator substrate and including a plurality ofterminals, the switch section configured to switch connections among theplurality of terminals according to the plurality of the controlsignals.
 18. The device according to claim 17, wherein a gate length ofthe second MOSFET is longer than a gate length of the first MOSFET. 19.The device according to claim 17, wherein a gate length of the thirdMOSFET is longer than a gate length of the first MOSFET.
 20. The deviceaccording to claim 17, wherein an absolute value of a threshold voltageof the second MOSFET is larger than an absolute value of a thresholdvoltage of the first MOSFET.
 21. The device according to claim 17,wherein an absolute value of a threshold voltage of the third MOSFET islarger than an absolute value of a threshold voltage of the firstMOSFET.
 22. The device according to claim 17, further comprising: adecoder configured to decode the parallel data and supply decoded datato the driver.
 23. The device according to claim 17, wherein the firstMOSFET has a lower breakdown voltage than the second MOSFET.
 24. Thedevice according to claim 17, wherein the first MOSFET has a lowerbreakdown voltage than the third MOSFET.
 25. The device according toclaim 17, wherein the first MOSFET has a smaller layout area than thesecond MOSFET.
 26. The device according to claim 17, wherein the firstMOSFET has a smaller layout area than the third MOSFET.
 27. The deviceaccording to claim 17, further comprising: a power supply pad providedon the silicon-on-insulator substrate on a first side of the interface,the power supply pad for supplying power to the interface; and a groundpad provided on the silicon-on-insulator substrate on a second side ofthe interface opposite the first side.
 28. The device according to claim17, wherein the interface, the first power supply, the driver, and theswitch section are included in a radio frequency switch device.
 29. Thedevice according to claim 28, wherein the plurality of terminalsincludes an antenna terminal and a plurality of radio frequencyinput/output terminals, and the switch section is configured to switchconnections among the plurality of terminals for transmitting andreceiving radio frequency signals by the antenna terminal.
 30. Thedevice according to claim 28, wherein a gate length of the second MOSFETis longer than a gate length of the first MOSFET.
 31. The deviceaccording to claim 28, wherein a gate length of the third MOSFET islonger than a gate length of the first MOSFET.
 32. The device accordingto claim 28, wherein the first MOSFET has a smaller layout area than thesecond MOSFET.
 33. The device according to claim 28, wherein the firstMOSFET has a smaller layout area than the third MOSFET.